Base Device
| Description |
| |
|
AZP51
|
Divide by 1 Sine to LVPECL Buffer
|
|
AZP52
|
Divide by 2 Sine to LVPECL Buffer
|
|
AZP53
|
Divide by 1,2 Sine to LVPECL Buffer
|
|
AZP54
|
Divide by 1 Sine to LVPECL Buffer
|
|
AZP92 | ECL/PECL
Divide by 1, 2 Clock Generation Chip with Selectable Enable |
|
AZP81
|
ECL/PECL
Filter-Based Multiplier & Limiting Amp with Selectable Enable
|
|
AZV99
|
PECL/LVDS
Oscillator Gain Stage & Buffer with Selectable Enable
|
|
AZ100LVEL32 | Divide by 2
Divider |
|
AZP94
|
ECL/PECL Divide by 1, 2 Clock Generation Chip with Tristate Compatible Outputs
|
|
AZP96
|
3V to 5.5V Differential Receiver with Minimized Input Loading
|
